what register stores the address of the next instruction to be executed

1.  In a CPU, what register stores the address of the next instruction to be executed.

2. The address of instruction currently being executed is found where in the CPU

3. If you encode the signed integer -11 into an 8 bit signed binary integer and then shift the bits to the right by two places AND wrap the bits (that fall off on the right) around to the left side of the word what is the resulting binary string. Express your answer in HEX.


4.What is the value of the following 2’s complement binary integer? 1011 1011

5. Cache is made up of small chunks of memory.  The Index + Tag + Data are referred to as the ____________

6. How many bits (8 bits/byte/primary color) are required to store the shades of every color using R-G-B encoding.  The display 256 by 128 pixels.

7.What is magnitude of the mixed BASE 8 decimal number 020.010 Express your

answer as a BASE 10 fraction.        

8 What Cache level is the fastest.

9. When you launch a excel app and then a second word app on your desktop at the same time with a single-core CPU, the CPU is performing in a manner known as ___________.

10. You add two negative non zero signed 4 bit binary integers.  The result has a 0 in the  left most position. The magnitude of one of the negative integers must at least be equal to ______________

11.  In problem 10 the magnitude of the smallest possible integer that solves the problem would have magnitude ______________

12. Encode the fraction 7 1/4  into 32 bit IEEE floating point format._________

13 How many general purpose registers exist in the CPU of the lc3

14 Decoding instructions in a superscalar architecture requires the replication of some of the electronics of what part of the CPU.____________

15. The hex value  x23 ( or 010 0011) is sent to the console screen. What symbol is displayed

16. The following is an lc3 instruction 1010011000001011 resides at address x4001.  The pointer to the data for this instruction is found at what address?

17. The cache controller uses the cache __________to determine whether a memory request already resides in cache.

18, In the lc3 the 16 bit data element xACCA is located at address x4000 (hex 4000). Address x300B holds the value x4000.  What instruction located at address x3008 will load the value xACCA into Register 3. Write the complete instruction in 16 binary ________________

19. If each memory location can be mapped to just one cache line. This mapping is an example of ______________ mapping.

20.  In a 2500 server farm, each server experiences an 8 minutes reboot time 1000 times a year. In addition, there are 200 repairs each year that average 1 hour each. After each repair the reboot, test and evaluation takes 15 minutes. What is the availability of the server farm. Express you answer in % out to 2 decimal places (eg  XX.YY%)

21/ The MAR is a Special purpose registers. It companion register contains what type of information.

22. What type of memory, is fast, close to the CPU and requires no electrical refresh circuitry.

23. In a RISC architecture all the opcodes are usually of the same length and            always have the same _______________.

24.    In a SMP system it is important to maintain cache coherency. Listening   for     cache events on    the memory bus shared by multiple processors is  referred to as __________

25. When a second instruction cannot be executed in parallel due to logic hardware limitations, this creates a pipeline event known as a _____________  ______________. (two words answer required).


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